 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| - 1 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) 256mbit gddr3 sdram revision 1.8 april 2005 samsung electronics reserves the right to change products or specification without notice. information in this document is provid ed in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for us e in life support, critical care, m edical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any government al procurement to which special terms or provisions may apply.
- 2 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) revision history revision 1.8 (april 9, 2005) - modified note description for the write latency on page 47. revision 1.7 (jan. 18 , 2005) - added lead free package part number in the data sheet. revision 1.6 (dec 2 , 2004) - changed icc2p and icc6 for all frequency. separted icc6 for -gc and -gl. revision 1.5 (oct 5 , 2004) - added k4j55323qf-g(v)c15 - timing diagram corrected on page 28 revision 1.4 (july 9 , 2004) - added k4j55323qf-g(v)l20 which is vdd&vddq=1.8v(typical) revision 1.3 (june 14 , 2004) - changed dc spec value for all the frequency. refer to the dc characteristics of page 45. - removed -gc12 from the spec. revision 1.2 (february 18 , 2004) - changed vdd/vddq from 1.9v+ 0.1v to 2.0v+ 0.1v in all frequencies. - dc changes : refer to the dc characteristics of page 45. revision 1.1 (january 29 , 2004) - typo corrected revision 1.0 (january 15 , 2004) - changed vdd/vddq of k4j55323qf-gc12 from 2.1v+ 0.1v to 1.9v+ 0.1v - changed vdd/vddq of k4 j55323qf-gc14/16/20 from 1.8v+ 0.1v to 1.9v+ 0.1v - changed tck(max) from 3.0ns to 3.3ns - dc spec finalized. typo corrected - 3 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) revision history revision 0.5 (january 7 , 2004) - preliminary spec - added "dummy mrs" command during the power-up sequence. typo corrected revision 0.4 (december 10 , 2003) - preliminary spec - typo corrected - added k4j55323qf-gc12 (800mhz) in the spec - key ac parameter changes : refer to the ac spec table on page 46,47 . added tdal in the ac characteristics table, . added ac parameter of -gc12 in the ac characteristics table, . changed trc of -gc14 from 31tck to 30tck, . changed trfc of -gc16 from 34tck to 33tck, - dc changes : refer to the dc characteristics table of page 45. - capacitance table change : refer to the capacitance table of page 45. revision 0.3 (november 13, 2003) - target spec - typo corrected - removed 800mhz from the spec - changed icc6 from 4ma to 7ma - key ac parameter changes : refer to the ac spec table on page 46,47 . changed twr of -gc14 from 6tck to 9tck, . changed twr of -gc16 from 5tck to 8tck, . changed twr of -gc20 from 4tck to 6tck . changed tpdex and txsr at low power from 100tck to 300tck revision 0.2 (october 17, 2003) - target spec - typo corrected revision 0.1 (september 26, 2003) - target spec - typo corrected revision 0.0 (september 25, 2003) - target spec - 4 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) ? 2.0v + 0.1v power supply for device operation ? 2.0v + 0.1v power supply for i/o interface ? on-die termi nation (odt) ? output driver strength adjustment by emrs ? calibrated output drive ? pseudo open drain compatible inputs/outputs ? 4 internal banks for concurrent operation ? differential clock inputs (ck and ck ) ? commands entered on each positive ck edge ? cas latency : 5, 6, 7, 8 and 9 (clock) ? additive latency (al): 0 and 1 (clock) ? programmable burst length : 4 ? programmable write latency : 1, 2, 3, 4, 5 and 6 (clock) ? single ended read strobe (rdqs) per byte ? single ended write strobe (wdqs) per byte general description features ? rdqs edge-aligned with data for reads ? wdqs center-aligned with data for writes ? data mask(dm) for masking write data ? auto & self refresh mode ? auto precharge option ? 32ms, auto refresh (4k cycle) ? 144 ball fbga ? maximum clock frequency up to700mhz ? maximum data rate up to 1.4gbps/pin ? dll for outputs 2m x 32bit x 4 ba nks graphic double data rate 3 synchronous dram with uni-directional data strobe ordering information *k4j55323qf-gl20/vl20 : vdd & vddq = 1.8v+ 0.1v(1.7v ~ 1.9v) *k4j55323qf-v is the lead free package part number part no. max freq. max data rate interface package K4J55323QF-GC14 700mhz 1400mbps/pin pseudo open drain 144 - ball fbga k4j55323qf-gc15 667mhz 1334mbps/pin k4j55323qf-gc16 600mhz 1200mbps/pin k4j55323qf-gc20* 500mhz 1000mbps/pin the 8mx32 gddr3 is 268,435,456 bits of hyper synchronous data rate dynamic ram organized as 4 x 2,097,152 words by 32 bits, fabricated with samsung ?s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 5.6gb/ s/chip. i/o transactions are possible on both edges of the clock cycle. range of operating frequencies, and programmable latencies allow the devi ce to be useful for a variet y of high performance memory system applications. for 2m x 32bit x 4 bank gddr3 sdram - 5 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) pin configuration note : 1. rfu1 is reserved for a12 2. rfu2 is reserved for ba2 3. (m,13) vref for cmd and address 4. (m,2) vref for data input dq23 a3 vdd vss rfu 2 vdd vdd rfu 1 vss vdd a4 dq8 vref a2 a10 /ras reset cke rfu5 zq /cs a9 a5 vref a0 a1 a11 ba0 /cas ck /ck /we ba1 a8/ap a6 a7 2345678910111213 b c d e f g h j k l m n wdqs0 rdqs0 vssq dq3 dq2 dq0 dq31 dq29 dq28 vssq rdqs3 wdqs3 dq4 dm0 vddq vddq dq1 vddq vddq dq30 vddq vddq dm3 dq27 dq6 dq5 vssq vssq vssq vdd vdd vssq vssq vssq dq26 dq25 dq7 rfu3 vdd vss vssq vss vss vssq vss vdd rfu4 dq24 dq17 dq16 vddq vssq vssq vddq dq15 dq14 nc, vss nc, vss nc, vss nc, vss dq19 dq18 vddq vssq vssq vddq dq13 dq12 nc, vss nc, vss nc, vss nc, vss wdqs2 rdqs2 vddq vssq vssq vddq rdqs1 wdqs1 nc, vss nc, vss nc, vss nc, vss dq20 dm2 vddq vssq vssq vddq dm1 dq11 nc, vss nc, vss nc, vss nc, vss dq21 dq22 vddq vssq vss vss vss vss vssq vddq dq9 dq10 normal package (top view) - 6 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. cmd, add inputs are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buff- ers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power- down. input buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm0 ~dm3 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write acce ss. dm is sampled on both edges of clock. although dm pins are input only, the dm loadi ng matches the dq and dqs loading. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 also determines if the mode register or extended mode r egister is to be accessed during a mrs or emrs cycle. a0 ~ a11 input address inputs: provided the row address for active co mmands and the column address and auto pre- charge bit for read/write commands to select one location out of the memory array in the respective bank. a8 is sampled during a precharge command to determine whether the precharge applies to one bank (a8 low) or all banks (a8 high). if only one bank is to be prec harged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during mode register set commands. row addresses : ra0 ~ ra11, column addresses : ca0 ~ ca7, ca9 . column address ca8 is used for auto precharge. dq0 ~ dq31 input/ output data input/ output: bi-directional data bus. rdqs0 ~ rdqs3 output read data strobe: output with read data. rdqs is edge-aligned with read data. wdqs0 ~ wdqs3 input write data strobe: input with write data. wdqs is center-aligned to the input data. nc/rfu no connect: no internal electrical connection is present. v ddq supply dq power supply: 2.0v 0.1v v ssq supply dq ground v dd supply power supply: 2.0v 0.1v v ss supply ground v ref supply reference voltage: 0.7*vddq , 2 pins : (m,2) for data input , (m,13) for cmd and address zq reference resistor connection pin for on-die termination. the value of resistor = 240 ? res input reset pin: reset pin is a vddq cmos input - 7 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) block diagram (2mbit x 32i/o x 4 bank) bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 2m x 32 2m x 32 2m x 32 2m x 32 sense amp 4-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ick addr lcke ick cke cs ras cas we dmi ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr 128 32 32 lwe ldmi x32 dqi input buffer 128 output dll * ick : internal clock input buffer rdqs wdqs - 8 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) self auto idle mrs emrs row precharge power write power act read a read refs refsx refa ckel mrs ckeh ckeh ckel write power applied automatic sequence command sequence read a write a read pre pre pre pre refresh refresh down power down active on a read a read a write a preall active precharge precharge preall read write preall = precharge all banks mrs = mode register set emrs = extended mode register set refs = enter self refresh refsx = exit self refresh refa = auto refresh ckel = enter power down ckeh = exit power down act = active write a = write with autoprecharge read a = read with autoprecharge pre = precharge functional description simplified state diagram write - 9 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) initialization gddr3 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. 1. apply power and keep cke/reset at low state ( all other inputs may be undefined) - apply vdd and vddq simultaneously - apply vddq before vref. ( i nputs are not recognized as valid until after v ref is applied ) 2. required minimum 100us for the stabl e power before reset pin transition to high - upon power-up the address/command active terminat ion value will automatically be se t based off the state of reset and cke. - on the rising edge of reset the cke pin is latched to determine the address an d command bus termination value. if cke is sampled at a zero the address termination is set to 1/2 of zq. if cke is sampled at a one the address termination is set to zq. - reset must be maintained at a logic low level and cs at a logic high value during powe r-up to ensure that the dq outp uts will be in a high-z state, all active terminators off, and all dlls off. 4. minimum 200us delay required prior to appl ying any executable command after stable power and clock. 5. once the 200us delay has been satisfied, a deselect or nop command should be applied, then reset and cke should be brought to high, 6. issue a precharge all command following after nop command. 7. issue a dummy mrs command ("00001000100001") 8. issue a emrs command (ba1ba0="01") to enable the dll. 9. issue mrs command (ba0ba1 = "00") to re set the dll and to program the operating parameters. 20k clock cycles are required to lock the dll. 9. issue a precharge all command 10 . issue at least two auto refresh command to updat e the driver impedance and calibrate the output drivers. following these requirements, the gddr 3 sdram is ready for normal operation. code v dd v ddq v ref ck ck res cke cke command dm a0-a7, a9-a11 a8 ba0, ba1 rdqs wdqs dq ra code code bao=l, nop pre dummy emrs mrs pre ar ar high high high ba1 =l bao=l, ba1 =l t=10ns power-up: v dd and ck stable t = 200us trp tmrd trfc trp trfc load extended mode register tmrd 20k cycle load mode register t is t ih code t is t ih t is t ih t is t ih t is t ih t is t ih t0 t1 ta0 tb0 tc0 td0 te0 tf0 t ats t ath t ch t cl t is t ih precharge all banks precharge all banks 1st auto refresh 2nd auto refresh dll reset all banks all banks code bao=h, ba1 =l t is t ih code t is t ih t is t ih ra ba tmrd act mrs load mode register (dummy mrs) - 10 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) 0 the mode register stores the data for controlling the va rious operating modes of gddr 3 sdram. it programs cas latency, addressing mode, test mode and various vendor spec ific options to make gddr3 s dram useful for variety of dif- ferent applications. the default value of the mode register is not defined, therefore the mode register must be written after emrs setting for proper operation. the mode register is written by asserting low on cs , ras , cas and we (the gddr3 sdram should be in active mode with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 11 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum six clock cycles are requested to co mplete the write operation in the mode register. the mo de register co ntents can be changed using the same command and clock cycle requirem ents during operation as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a 0 ~ a 2 . cas latency (read latency from column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 8 is used for dll reset. a 9 ~ a 11 are used for write latency. refer to the table for specific codes for various addressing modes and cas latencies. mode register set(mrs) cas latency a 6 a 5 a 4 cas latency 000 8 001 9 010 reserved 011 reserved 100 reserved 101 5 110 6 111 7 ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 test mode a 7 mode 0 normal 1test burst type a 3 burst type 0 sequential 1 reserved dll a 8 dll reset 0no 1yes 0 0 wl dll tm cas latency bt burst length burst length a 2 a 1 a 0 burst length 0 0 0 reserved 0 0 1 reserved 010 4 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved ba 0 a n ~ a 0 0mrs 1emrs write latency a 11 a 10 a 9 write latency 000 reserved 001 1 010 2 011 3 100 4 101 5 110 6 111 reserved - 11 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) 0 burst length read and write accesses to the gddr3 sdra m are burst oriented, with the burst l ength being programmable, as shown in mrs table. the burst length determines the maxi mum number of column locations that can be accessed for a given read or write com- mand. burst length of 4 only is available. reserved states should not be used, as unknown operation or incompatibility with fut ure ver- sions may result. when a read or write co mmand is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place with in the block, meaning that the burst will wrap within the block if a boundary is reached . the block is uniquely selected by a2-a i when the burst length is set to four (where a i is the most significant column address bit for a given config- uration). the remaining (least significant) a ddress bit(s) is (are) used to select t he starting location within the block. the programmable burst length applies to both read and write bursts. burst type accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bi t a3. this device does not support the interleaved burst mode found in ddr sdram devices . the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in below table: burst definition burst definition burst length starting column address order of access within a burst type= sequential 4 a1 a0 0 0 0 - 1 - 2 - 3 note : 1. for a burst length of four, a2-a 7 select the block of four burst; a0-a1 se lect the starting column within the block and must be set to zero programmable impedance output buffer and active terminator the gddr3 sdram is equipped with programmabl e impedance output buffers and active terminat ors. this allows a user to match the driver impedance to the system. to adjus t the impedance, an external precision resi stor(rq) is connect ed between the zq pin and vss. the value of the resistor must be six times the desired output impedance. for example, a 240 ? resistor is required for an output impedance of 40 ? . to ensure that output impedance is one sixth the value of rq (within 10 %), the range of rq is 120 ? to 360 ? (20 ? to 60 ? output impedance). res, ck and /ck are not internally terminat ed. ck and /ck will be terminated on the syst em module using external 1% resisters. the output impedance is updated during all auto refresh commands and nop co mmands when a read is not in progress to compen- sate for variations in supply voltage and temperature. the output impedance updates are transpar ent to the system. impedance up dates do not affect device operation, and all data sheet timing and curr ent specifications are met during an update. to guarantee opt imum out- put driver impedance after power-up, the gd dr3(x32) needs 20us after the clock is appli ed and stable to calibrate the impedance upon power-up. the user can operate the part with fewer than 20us, but optimal output im pedance is not guaranteed. the value of zq i s also used to calibrated the internal address/comm and termination resisters. the two terminat ion values that are selectable at power up are 1/ 2 of zq and zq. the value of zq is used to calibrate the internal dq termination resisters. the two termination values that are select- able are 1/4 of zq and 1/2 of zq. - 12 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) 0 cas latency (read latency) the cas latency is the delay, in clock cycles, between the regi stration of a read command and the availability of the first bi t of output data. the latency can be set to 5~9 clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . below table indicates the operating fr equencies at which each cas latency set- ting can be used. reserved states should not be used as unknown operation or incompatib ility with future versions may result. cas latency allowable operating frequency (mhz) speed cl=9 cl=8 cl=7 cl=6 cl=5 -12 800---- -14 700 - - - - -16 - 600 - - - -20 - - 500 - - nop nop nop read t0 t3 t5 t5n /ck ck command t4 rdqs dq cl = 5 nop nop nop read t0 t4 t6 t6n /ck ck command t5 rdqs dq cl = 6 burst length = 4 in the cases shown shown with nominal t ac and nominal t dsdq don?t care transitioning data - 13 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) write latency the write latency (wl) is the delay, in clock cycles, between the registration of a write command and the availability of the first bit of input data. the latency can be set from 1 to 6 clocks depending in the operating fr equency and desired current draw. when the w rite latencies are set to 1 or 2 or 3 clocks, the input receivers nev er turn off when the write comm and is registered. if a write co mmand is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . reserved states should not be used as unknown operation or in compatibility with future versions may result. * maximum frequency of gddr3 can be limited in wl4, 5 and 6 nop nop nop write t0 t1 t3 t3n /ck ck command t2 dq wl = 3 nop nop nop write t0 t2 t4 t4n /ck ck command t3 dq wl = 4 burst length = 4 in the cases shown don?t care transitioning data wdqs wdqs - 14 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) 0 test mode the normal operating mode is selected by issuing a mode regist er set command with bits a7 set to zero, and bits a0-a6 and a8- a11 set to the desired values. test mode is entered by issuing a mo de register set command with bit a7 set to one, and bits a0- a6 and a8-a11 set to the desired values. test mode functions ar e specific to each dram manufac turer and its exact functions are hidden from the user. dll reset the normal operating mode is selected by issuing a mode regist er set command with bit a8 set to zero, and bits a0-a7 and a9- a11 set to the desired values. a dll reset is initiated by issuing a mode register set command with bit a8 set to one, and bits a0- a7 and a9-a11 set to the desired values. when a dll reset is comple te the gddr3 sdram reset bit 8 of the mode register to a zer o. after dll reset mrs, power down can not be issued during 10 clock. - 15 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) the extended mode register stores the data output driver strength and on-die termination options. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0(the gddr3 sdram should be in all bank precharge with cke already high prior to writing into the extended mode regis- ter). the state of address pins a0 ~ a11 and ba0 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. six clock cycles are required to complete the write operation in the extended mode register. 4 kinds of the output driver strength are supported by emrs (a1, a0) code. the mode register contents can be changed using the same command and clock cycle requirements during opera- tion as long as all banks are in the idle state. "high" on ba0 is used for emrs. refer to the table for specific codes. extended mode register set(emrs) ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dll a 6 dll 0 enable 1 disable additive latency a 9 a 8 al 00 0 01 1 10reserved 11reserved 0 1 lp id al twr dll twr termination drive strength ba 0 a n ~ a 0 0mrs 1emrs low power a 11 low power 0 disable 1 enable vendor id a 10 vendor id 0off 1on twr a 7 a 5 a 4 twr 000 3 001 4 010 5 011 6 100 7 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved drive strength a 1 a 0 drive strength 0 0 autocal 01 30 ? 10 40 ? 11 50 ? termination a 3 a 2 termination 00odt disabled 01 reserved 10 zq/4 11 zq/2 * zq : resistor connection pin for on-die termination - 16 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) 0 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after disabling the dll for debugging or evaluation. (when the device exits self refresh mode, the dll is enabled automatically.) any time th e dll is enabled, 20k clock cycles must occur before a read command can be issued. data termination the data termination, dt, is used to determine the value of the internal data termination resisters. the gddr3 sdram supports 60 ? and 120 ? termination. the termination may also be disabled for testing and other purposes. data driver impedance the data driver impedance (dz) is used to determine the value of the data drivers impedance. when autocalibration is used the data driver impedance is set to 40 ? s and it?s tolerance is determined by the calibration accuracy of the device. when any other value is selected the target impedance is set nominally to the desired impedance. however, the accuracy is now determined by the device?s specific proce ss corner, applied voltage and operating temperature. additive latency the additive latency function (al) is used to optimize the command bus efficiency. the al value is used to determine the number of clock cycles that is to be added to cl after cas is captured by the ri sing edge of ck. thus the total cas latency is determined by adding cl and al. manufacturers vendor code an d revision identification the manufacturers vendor code, v, is selected by issuing a extended mode register set command with bits a10 set to one, and bits a0-a9 and a11 set to the desired values. when the v function is enabled the gddr3 sdram will pro- vide its manufacturers vendor code on dq[3:0 ] and revision identi fication on dq[7:4] manufacturer dq[3:0] reserved 0 samsung 1 infineon 2 elpida 3 etron 4 nanya 5 manufacturer dq[3:0] hynix 6 mosel 7 winbond 8 esmt 9 reserved a reserved b manufacturer dq[3:0] reserved c reserved d reserved e micron f - 17 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) 0 low power mode can be enabled by a11="h" during the emrs command and in this case, precharge power down command activates lp mode1 and self refresh command activates lp mode2. in case that a11 set to "l" during the emrs, low power mode is disabled and precharge power down command and self refresh command will do normal operation. if a precharge power down command issued under the condition of low power mode enabled, a device enters the lp mode1 and it can reduce precharge powe r down current significantly by disabling dll during the precharge power down, however it requires more time to exit power down. if the power down duration is less than 20us, the required tpdex is 300tck. otherwise, 20000tck required for the tpdex. if a self refresh command issued under the condition of low power mode enabled, a device enters the lp mode2 and it can reduce txsr while slightly increase the self refresh current. if the self refresh duration is less than 20us, the required txsr is 300tck. otherwise, 20000tck required for the txsr. low power mode low power command disabled (a11="l" @ emrs) enabled (a11="h" @ emrs) comments precharge power down precharge power down lp mode1 . dll disabled for the purpose of current saving ( icc2p minimized) . tpdex increased - 300tck@ power down exit within 20us - 20ktck@ power down exit after 20us self refresh self refresh lp mode2 . short txsr - 300tck@ self refresh exit within 20us - 20ktck@ self refresh exit after 20us - 18 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) truth table - commands truth table - dm operation name (function) cs ras cas we addr notes deselect (nop) h x x x x 8, 11 no operation (nop) l h h h x 8 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, and start write burst) l h l l bank/col 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (ent er self refresh mode) l l l h x 6, 7 load mode register l l l l op-code 2 data terminator disable x h l h x name (function) dm dqs notes write enable l valid write inhibit h x 10 1. cke is high for all commands except self refresh. 2. ba0~ba1 select either the mode register or the ex tended mode register (ba0=0, ba1 =0 select the mode register; ba0=1, ba1=0 select extended mode register; other comb inations of ba0~ba1 are reserved). a0~a11 provide the op-code to be written to the selected mode register. 3. ba0~ba1 provide bank address and a0~a11 provide row address. 4. ba0~ba1 provide bank address; a0~a7 and a9 provide co lumn address; a8 high enabl es the auto precharge feature (nonpersistent) , and a8 low disables the auto precharge feature. 5. a8 low : ba0~ba1 determine which bank is precharged. a8 high : all banks are precharged and ba0~ba1 are "don?t care." 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressi ng; ll inputs and i/os are "don?t care" except for cke. 8. deselect and nop are functionally interchangeable. 9. cannot be in powerdown or self-refresh state. 10. used to mask write data ; provided coincident with the corresponding data. 11. except data termination disable. note : commands below truth table-commands provides a quick reference of available commands. this is followed by a verbal descrip- tion of each command. two additional truth tables appear following the operation section : these tables provide current state/next state information. - 19 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) 0 deselect the deselect function (/cs high) prevents new command s from being executed by t he ddr(x32). the gddr3(x32) sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct se lected gddr3(x32) to perform a nop (/cs low). this pre- vents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs a0-a11. see mode r egister descriptions in the register definition section. the load mode register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tmrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0,ba1 inputs selects the bank, and the address provided on in putsa0-a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a7, a9 selects the starting column location. the value on input a8 deter- mines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a7, a9 selects the starting column location. the value on inputs a8 deter- mines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not select ed, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low. the correspondin g data will be written to memory ; if the dm signal is regis- tered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a8 determines whether one or all banks are to be precharged, and in the case where only one banks are to be pre- charged, inputs ba0,ba1 select the bank. otherwise ba0, ba1 are treated as "don?t care." once a bank has been pre- charged, it is in the idle state and must be activated prio r to any read or write command will be treated as a nop if there is no open row is already in the process of precharging. - 20 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) auto precharge auto precharge is a feature which performs the same indi vidual-bank precharge function described above, but without requiring an explicit command. this is accomplished by using a8 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is auto- matically performed upon completion of the read or write burs t. auto precharge is nonpersis tent in that it is either enable or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid state within a burst. this "earliest valid stage" is determined as if an explicit precharge command was issued at the earliest possible time, without violating t ras(min) , as described for each burst type in the operation sec- tion of this data sheet. the user must not issue anot her command to the same bank until the precharge time(t rp ) is com- pleted. auto refresh auto refresh is used during normal operation of the gddr3 sdram and is analogous to /cas-before-/ras (cbr) refresh in fpm/edo drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a "don?t care" during an auto refresh command. the 256m b(x32) ddr2(x32) requires auto refresh cycles at an average interval of 7.8us (maximum). a maximum of eight auto refresh commands can be posted to any given gddr3(x32) sdram , meaning that the maxi- mum absolute interval between any auto refresh command and the next auto refresh command is 9 x 7.8us(70.2us). this maximum absolute interval is to allow gddr3(x32) sdram output drivers and internal terminators to automatically recalibrate compensating for voltage and temperature changes. self refresh the self refresh command can be used to retain data in the g ddr3(x32) sdram ,even if th e rest of the system is powered down. when in the self refresh mode,the gddr3(x32) sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). the dll is automati- cally disabled upon entering self refresh and is automatically enabled and reset upon exiting self refresh. the active termination is also disabled upon en tering self refresh and en abled upon exiting self re fresh. (200 clock cycles must then occur before a read comma nd can be issued). input signals except cke are "don?t care" during self refresh. the procedure for exiting self refresh requires a sequence of commands. first, ck and /ck must be stable prior to cke going back high. once cke is high,the gd dr3(x32) must have nop commands issued for txsnr because tine is required for the completion of any internal refr esh in progress. a simple algorithm for meeting both refresh, dll requirements and out-put ca libration is to apply nops for 200 clock cycl es before applying any other command to allow the dll to lock and the output drivers to recalibrate. data terminator disable (bus snooping for read command) the data terminator disable command is detected by the device by sn ooping the bus for read commands excluding /cs. the gddr3 dram will disable its data termi nators when a read command is detected. the terminators are disable cl-1 clocks after the read co mmand is detected. in a two rank system both dram devices will snoop the bus for read commands to either device and both will disable their terminators if a read command is detected. the com- mand and address terminators and always enabled. - 21 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) on-die termination bus snooping for read commands other than /cs is used to control the on-die termination. the gddr3 sdram will dis- able the on-die termination when a read command is detected, regardless of the state of /cs. the on-die termination is disabled x clocks after the read command where x eq uals cl-1 and stay off for a durati on of bl/2 + 2, as below figure, data termination disable timing. in a two-rank system, both dram devices snoop the bus for read commands to either device and both will disable the on-die termination if a read command is detected. the on-die termination for all other pins on the device are always on for both a single-rank system and a dual-rank system. the on-die termination value on address and control pins is dete rmined during power-up in relation to the state of cke on the first transition of reset. on the rising edge of reset, if cke is sampled low, then the configuration is determined to be a single-rank system. the on-d ie termination is then set to one-half zq for t he address pins. on th e rising edge of reset, if cke is sampled high, then th e configuration is determined to be a d ual-rank system. the on-die termination for the dqs, wdqs, and dm pi ns is set in the emrs. nop nop nop nop nop read t0 t7 t8 t8n t9 t9n t10 t11 ck# ck command address rdqs dq bank a, col n cl = 8 do n dq termination gddr3 data termination is disabled data termination disable timing note : 1. do n = data-out from column n . 2. burst length = 4. 3. three subsequent elements of data-out appear in the specified order following do n . 4. shown with nominal t ac and t dqsq . 5. rdqs will start driv ing high one-half cycle prior to the first falling edge. 6. the data terminators are disabled starting at cl-1 and the duration is bl/2 + 2 7. reads to either rank disable bot h ranks? termination regardles s of the logic level of /cs. don?t care transitioning data - 22 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) operations bank/row activation before any read or write commands can be issued to a banks within the gddr3 sdram, a row in that bank must be "opened." this is accomplished via the active command, which selects both the bank and the row to be activated. after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command in which a r ead or write command can be entered. for example, a t rcd specification of 16ns wit h a 450mhz clock (2.2ns period) results in 7. 2 clocks rounded to 8. this is reflected in below figure, which covers any case where 7 - 24 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) t0 t1 t2 t2n t3 t3n t4 ck# ck rdqs 1.6 dq(last data valid) dq(first data no longer valid) all dqs and rdqs, collectively 5 t ch t dqsq 2 (max) t cl t2 t2n t3 t3n t2 t2n t3 t3n t2 t2n t3 t3n t dqsq 2 (min) t dqsq 2 (max) t dqsq 2 (min) t dqsh 4 t dqsh 4 t dv 4 t dv 4 t dv 4 t dv 4 data output timing (1) - t dqsq , t qh and data valid window data output timing (2) - t dqsq , t qh and data valid window t0 t1 t2 t2n t3 t3n t4 ck# ck rdqs 1.6 all dqs and rdqs, collectively 5 t2 t2n t3 t3n t dqsh 4 t dqsh 4 t2 t2n t3 t3n t ac (max) t dqsh 4 t dqsh 4 t ac (min) all dqs and rdqs, collectively 5 rdqs 1.6 t ch t cl note : 1. t dqsq represents the skew between the 8 dq lines and the respective rdqs pin. 2. t dqsq is derived at each rdqs clock edge and is not cumulative over time and begins with first dq transition and ends with the last valid transition of dqs. 3. t ac is show in the nominal case 4. t dqhp is the lesser of tdqsl or tdqsh strobe transition collec tively when a bank is active. 5. the data valid window is derived for each rdqs transitions and is defined by t dv . 6. there are 4 rdqs pins for this device with rdqs0 in relation to dq0-dq7, rdqs1 in relation dq8-dq15, rdqs2 in relation to dq16-24 and rdqs3 in relation to dq25-dq31. 7. this diagram only represents one of the four byte lanes. 8. t ac represents the relationship between dq, rdqs to the crossing of ck and /ck. - 25 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) nop nop nop nop nop read t0 t7 t8 t9 t9n t10 t11 /ck ck command address rdqs dq bank a, col n cl = 9 do n 1. do n =data-out from column n . 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n . 4. shown with nominal t ac and t dqsq. 5. rdqs will start driving high 1/2 cl ock cycle prior to the first falling edge. note : don?t care transitioning data read burst nop nop nop nop nop read t0 t7 t8 t8n t9 t9n t10 t11 /ck ck command address rdqs dq bank a, col n cl = 8 do n - 26 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) consecutive read bursts nop nop read nop nop read t0 t1 t2 t8 t8n t9 t10 /ck ck rdqs dq bank a, col n cl = 8 do n bank a, col b t10n t9n do b command address 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n . 4. three subsequent elements of data-out appear in the programmed order following dq b . 5. shown with nominal t ac and t dqsq. 6. example applies when read commands are issued to different devices or nonconsecutive reads. 7. rdqs will start driving high one half-clock cy cle prior to the first falling edge of rdqs. note : don?t care transitioning data - 27 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) nonconsecutive read bursts don?t care transitioning data nop nop nop read nop read t0 t7 t8 t8n t9 t9n t10 t17 /ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, col b t17n t18 nop do b 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n . 4. three subpsequent elements of data-out appear in the programmed order following dq b . 5. shown with nominal t ac and t dqsq. 6. example applies when read comm ands are issued to different devices or nonconsecutive reads. 7. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. note : - 28 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) random read accesses don?t care transitioning data note : nop nop read nop nop read t0 t1 t2 t8 t8n t9 t10 /ck ck command address rdqs dq bank a, col n cl = 8 do n bank a, col b t10n t9n do b do n do n do n nop nop read nop nop read t0 t1 t7 t8 t8n t9 t10 /ck ck rdqs dq bank a, col n cl = 8 bank a, col b t10n t9n command address 1. do n (or x or b or g ) = data-out from column n (or column x or column x or column b or column g ). 2. burst length = 4 3. n ? or x or b ? or g ? indicates the next data-out following do n or do x or do b or do g , respectively 4. reads are to an active row in any bank. 5. shown with nominal t ac and t dqsq. 6. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. do n do n do n do n - 29 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) read to write read to write don?t care transitioning data note : 1. do n = data-out from column n . 2. di b = data-in from column b . 3. burst length = 4 4. one subsequent element of data-out appears in the programmed order following do n . 5. data-in elements are applied following di b in the programmed order. 6. shown with nominal t ac and t dqsq. 7. t dqss in nominal case. 8. rdqs will start driving high one half-clock cycle prior to the first falling edge of rdqs. 9. the gap between data termination enable to t he first data-in should be greater than 1tck nop nop write nop nop read t0 t7 t8 t9 t9n t10 t11 /ck ck command address rdqs dq bank col n cl = 8 dm t8n do n di b t wl = 4 wdqs dq nop t12 t12n bank a, col b 1tck < termination dq termination disabled dq termination enbaled - 30 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) read to precharge don?t care transitioning data note : nop nop pre nop act read t0 t1 t2 t8 t8n t9 t10 /ck ck command address rdqs dq bank a, col n cl = 8 do n bank a t9n bank a, row t rp 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out appear in the programmed order following dq n. 4. read to precharge equals two clocks, wh ich enables two data pairs of data-out. 5. shown with nominal t ac and t dqsq. 6. example applies when read comm ands are issued to different de vices or nonconsecutive reads. 7. rdqs will start driving high one half-clock cy cle prior to the first falling edge of rdqs. - 31 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) writes write bursts are initiated with a write command, as shown in figure. the starting column and bank addresses are provided with the write command, and auto precharge is ei ther enabled or disabled for that access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered in a rising edge of wdqs following the write latency set in the mode register and subsequent data elements will be registered on successive edges of wdqs. prior to the first valid wdqs edge a half cycle is needed and spec- ified as the write preamb le; the half cycle in wd qs following the last data-in element is known as the write postamble. the time between the write command and the first valid falling edge of wdqs (t dqss ) is specified with a relative to the write latency. all of the write diagrams show the nominal case, and where the two extreme cases (i.e., t dqss(min) and t dqss(max) ) might not be intuit ive, they have also been included. write burst figure shows the nominal case and the extremes of tdqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored. data for any write burst may not be truncated with a subsequent write command. the new write com- mand can be issued on any positive edge of clock following the previous write command after the burst has completed. the new write com- mand should be issued x cycles after the first write command should be equals the number of desired nibbles (n ibbles are required by 4n-prefetch architecture). an example of nonconsecutive writes is shown in nonconsecutive write to read figure. full-speed random write accesses within a page or pages can be performed as shown in random write cycl es figure. data for any write burst may be followed by a subsequent read command. data for any write burst may be followed by a subsequent pre- charge command. to follow a write the write burst, t wr should be met as shown in writ e to precharge figure. data for any write burst can not be truncated by a subsequent pre- charge command. /ck ck ca en ap dis ap ba /cs /ras /cas /we a0-a7, a9 a10, a11 a8 ba0,1 cke high write command ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharge don?t care - 32 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) nop nop nop nop nop write t0 t1 t2 t3 t3n t4 t5 /ck ck command address bank a, col b t dqss nop t4n t5n t6 dq dm di b wdqs di b di b t dqss (nom) dq dm wdqs t dqss (min) dq dm wdqs t dqss (max) t dqss t dqss write burst don?t care transitioning data note : 1. di b = data-in for column b. 2. three subsequent elements of data-in are appl ied in the programmed order following di b. 3. a burst of 4 is shown. 4. a8 is low with the write co mmand (auto precharge is disabled). 5. write latency is set to 4 di b di b di b di b di b di b di b di b di b - 33 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) consecutive write to write don?t care transitioning data note : nop nop write nop nop write t0 t1 t3 t3n t4 t5 ck# ck command address bank col b t dqss (nom) nop t4n t5n t6 dq dm wdqs t2 t6n t7 nop di b di n bank col n 1. di b , etc. = data-in for column b , etc. 2. three subsequent elements of data-in are app lied in the programmed order following di b . 3. three subsequent elements of data-in are app lied in the programmed order following di n . 4. burst of 4 is shown. 5. each write command may be to any bank of the same device. 6. write latency is set to 3 di b di b di b di n di n di n - 34 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) nonconsecutive write to write don?t care nop nop nop write nop write t0 t1 t3 t3n t4 t5 /ck ck command address bank, col b nop t4n t5n t6 dq dm di b wdqs t2 t6n t7 nop di n bank, col n t dqss (nom) don?t care transitioning data note : 1. di b, etc. = data-in for column b, etc. 2. three subsequent elements of data-in are app lied in the programmed order following di b. 3. three subsequent elements of data-in are app lied in the programmed order following di n. 4. burst of 4 is shown. 5. each write command may be to any bank. 6. write latency is set to 3 di b di b di b di n di n - 35 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) random write cycles don?t care transitioning data note : nop write nop nop write t0 t1 t3 t3n t4 t5 /ck ck command address bank col b t dqss (nom) nop t4n t5n t6 dq dm wdqs t2 t6n t7 nop di b di x bank col x write bank col g di b di b di b di x di x di x di g di g 1. di b, etc. = data- in for column b, etc. 2. b: etc. = the next data - in following di b. etc., accordi ng to the programmed burst order. 3. programmed burst length = 4 cases shown. 4. each write command may be to any bank. 5. last write command will have the rest of the nibble on t8 and t8n 6. write latency is set to 3 - 36 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) write to read don?t care transitioning data note : nop nop write nop nop write t0 t1 t3 t3n t4 t5 /ck ck command address bank col b t dqss nop t4n t6 dq dm wdqs t2 t10 read di b bank col b t18 t19 nop nop t dqss (nom) bank a. col n cl = 9 rdqs t dqss dq dm wdqs di b di n t dqss (min) cl = 9 rdqs di n t dqss dq dm wdqs di b di n t dqss (max) cl = 9 rdqs tcdlr = 5 t19n 1. di b = data-in for column b . 2. three subsequent elements of data-in the programmed order following di b. 3. a burst of 4 is shown. 4. t cdlr is referenced from the first positive ck edge after the last data-in pair. 5. the read and write commands are to the same device. however, t he read and write commands may be to different devices, in which case t cdlr is not required and the read command could be applied earlier. 6. a8 is low with the write command (auto precharge is disabled). 7. write latency is set to 3 - 37 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) write to precharge don?t care transitioning data note : nop nop write nop nop write t0 t1 t3 t3n t4 t5 /ck ck command address bank col b t dqss nop t4n t11 dq dm wdqs t2 t12 pre di b bank col b t13 t14 nop nop t dqss (nom) bank t dqss dq dm wdqs di b t dqss (min) t dqss dq dm wdqs di b t dqss (max) t wr t rp 1. di b = data-in for column b . 2. three subsequent elements of data- in the programmed order following di b . 3. a burst of 4 is shown. 4. a8 is low with the write command (auto precharge is disabled). 5. write latency is set to 3 - 38 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time (t rp ) after the pre- charge command is issued. input a8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as "don?t care." once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to the bank. power-down (cke not active) unlike sdrams,gddr3(x32) sdram requires cke to be active at all times an access is in progress; from the issuing of a read or write command until completion of the burst. for reads, a burst completion is defined when the read postamble is satisfied; for writes, a burst completion is de fined bl/2 cycles after the wr ite postamble is satisfied. power-down is entered when cke is registered low. if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and out- put buffers, excluding ck,/ck and cke. for maximum power savings, the user has the option of disabling the dll prior to entering power- down. however, power-down duration is limited by the refresh require- ments of the device, so in most appl ications,the self-refresh mode is pre- ferred over the dll-disabled power-down mode. when in power-down, cke low and a stable clock signal must be maintained at the inputs of the gddr3 sdram, while all other input sig- nals are "don?t care." the power-down state is synchronously exited when cke is registered high (in conjunct ion with a nop or deselec t command). a valid exe- cutable command may be ap plied six clock cycle later. all banks one bank ba /cs /ras /cas /we a0-a7, a9-a11 ba0,1 ba=bank address /ck ck cke high a8 don?t care (if a8 is low; otherwise "don?t care") precharge command nop nop nop valid t0 t1 ta0 ta1 ta2 /ck ck command valid ta 7 t2 cke t is t pdex t is no pead/write access in progress enter power - down mode exit power - down mode power-down nop - 39 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) truth table - clock enable (cke) notes : 1. cken is the logic state of cke at clock edge n ; cken-1was the state of cke at the previous clock edge. 2. current state is the state of the ddr2(x32) immediately prior to clock edge n . 3. commandn is the command registered at clock edge n , and action n is a result of command n 4. all state and sequence not shown are illegal or reserved. 5. deselect or nop commands sh ould be issued on any clock edges o ccurring during the t xsa period. cken-1 cken current state commandn actionn notes ll power-down x maintain power-down self refresh x maintain self refresh lh power-down deselect or nop exit power-down self refresh deselect or nop exit self refresh 5 hl all banks idle deselect or nop precharge power-down entry bank(s) active deselect or nop active power-down entry all banks idle auto refresh self refresh entry - 40 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) truth table - cu rrent state bank n - command to bank n notes : 1. this table applies when cke n-1 was high and cke n is high (see cke truth table) and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted (i.e., t he current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions : idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read : a read burst has been initiated, with auto precharge disabled. write : a write burst has been initiate d, with auto precharge disabled. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the ot her bank are determined by its current stat e and truth table- current state bank n - command to bank n . and according to truth table - current state bank n -command to bank m. precharging : starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating : starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the :row active" state. current state /cs /ras /cas /we command/ action notes any h x x x deselect (nop/ continue previous operation) 13 l h h h no operation (nop/continue previous operation) x h l h data terminator disable idle l l h h active (select and activate row) l l l h auto refresh 7 row active llllload mode register 7 l h l h read (select column and start read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read (auto-precharge disable) l h l h read (select column and start new read burst) 10 l h l l write (select column and start write burst) 10, 12 l l h l precharge (only after t he read burst is complete) 8 write (auto-precharge disabled) l h l h read (select column and start read burst) 10, 11 l h l l write (select column and start new write burst) 10 l l h l precharge (only after the write burst is complete) 8, 11 - 41 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) read w/ auto- : starts with registration of an read command with auto precharge enabled and ends precharge enabled when trp has been met. once t rp is met, the bank will be in the idle state. write w/ auto- : starts with registration of a write command with auto precharge enabled and ends precharge enabled when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command ; co mmand inhibit or nop commands must be applied on each positive clock edge during these states. refreshing : starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the ddr2(x32) will be in the all banks idle state. accessing mode : starts with registration of a load mode register command and ends when t mrd register has been met. once t mrd is met, the gddr3(x32) sdram w ill be in the all banks idle state. precharge all : starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. read or write : starts with registration of the active command and ends the last valid data nibble. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. may or may not be bank-specific ; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. left blank 10. reads or writes listed in the co mmand/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking. 12. a write command may be applied after the completion of the read burst. 13. except data termination disable. - 42 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) truth table - curr ent state bank n - command to bank m notes : 1. this table applies when cke n-1 was high and cke n is high (see truth table- cke ) and after t xsnr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, exce pt where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. current state /cs /ras /cas /we command/ action notes any h x x x deselect (nop/ continue previous operation) 8 l h h h no operation (nop/continue previous operation) x h l h data terminator disable idle xxxxany comm and otherwise allowed to bank m row activating, active, or prechrging l l h h active (select and activate row) l h l h read (select column and start read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge read (auto-precharge disable) l l h h active (select and activate row) l h l h read (select column and start new read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge write (auto-precharge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) 6, 7 l h l l write (select column and start new write burst) 6 l l h l precharge read (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 6 l h l l write (select column and start write burst) 6 l l h l precharge write (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) 6 l h l l write (select column and start new write burst) 6 l l h l precharge - 43 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) 3. current state definitions : idle : the bank has been precharged, and t rp has been met. row active : a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read : a read burst has been initiated, with auto precharge disabled. write : a write burst has been initiate d, with auto precharge disabled. read w/ auto- : see following text precharge enabled write w/ auto- : see following text precharge enabled 3a. the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts : the access period and the precharge period . for read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible pre- charge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when twr ends, with twr command and ends where the precharge period (or t rp ) begins. during the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, active, precharge, read and write commands to the other bank ma y be applied. in either case, all other related limitations apply (e.g., contention between read data write data must be avoided). 3b. the minimum delay from a read or write command with auto precharge enabled, to a command to a different bank is summarized below. 4. auto refresh and load mode register commands may only be issued when all banks are idle. 5. all states and sequences not shown are illegal or reserved. 6. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 7. requires appropriate dm masking. 8. except data termination disable from command to command minimum delay (with concurrent auto precharge) write w/ap read or read w/ap [wl + (bl/2)] tck + tcdlr write or write w/ap (bl/2) * tck precharge 1 tck active 1 tck read w/ap read or read w/ap (bl/2) * tck write or write w/ap [cl ru + (bl/2)] + 1 - wl * tck precharge 1 tck active 1 tck - 44 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) stresses greater than those listed under "absolute maximum ra tings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other c onditions above those indicated in the operat ional sections of this specificat ion is not implied. exposure periods may affect reliability. note : power & dc operating conditions recommended operating conditions (voltage referenced to 0 c tc 85 c ; vdd=2.0v + 0.1v, vddq=2.0v + 0.1v) note : 1.under all conditions, vddq must be less than or equal to vdd. 3. vref is expected to equal 70% of vddq for the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed + 2 percent of the dc value. thus, fr om 70% of vddq, vref is allowed + 25mv for dc error and an additional + 25mv for ac noise. 4. the dc values define where the input slew rate requirements are imposed, and the input signal must not violate the se levels in order to maintain a valid level. the inputs require the ac value to be achieved during signal transition edge and the driver shoul d achieve the same slew rate through the ac values. 5. input and output slew rate =3v/ns. if the input slew rate is less than 3v/ns, input timing may be compromised. all slew rate are measured between vih and vil. dq and dm input slew rate must not deviate from dqs by more than 10%. if the dq,dm and dqs slew rate is less tha n 3v/ns, timing is longer than referenced to the mid-point but to the vil(ac) maximum and vih(ac) minimum points. 6. vih overshoot : vih(max) = vddq + 0.5v for a pulse width 500ps and the pulse width can not be greater than 1/3 of the cycle rate. vil undershoot : vil(min)=0.0v for a pulse width 500ps and the pulse width can not be greater than 1/3 of the cycle rate. parameter symbol min typ max unit note device supply voltage v dd 1.9 2.0 2.1 v 1 output supply voltage v ddq 1.9 2.0 2.1 v 1 reference voltage v ref 0.69*v ddq - 0.71*v ddq v3 dc input logic high voltage v ih (dc) v ref +0.15 - - v 4 dc input logic low voltage v il (dc) --v ref -0.15 v 4 output logic low voltage v ol(dc) - - 0.76 v ac input logic high voltage v ih(ac) v ref +0.25 - - v 4,5,6 ac input logic low voltage v il(ac) --v ref -0.25 v 4,5,6 input leakage current any input 0v- - 46 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) dc characteristics note : 1. measured with outputs open and odt off 2. refresh period is 32ms 3. measured current at vdd & vddq = 2.0v parameter symbol test condition version unit -14 -15 -16 -20 operating current (one bank active) i cc1 burst length=4 t rc t rc (min). i ol =0ma, t cc = t cc (min). dq,dm,dqs inputs changing twice per clock cycle. address and control inputs changing once per clock cycle 505 500 495 485 ma precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 140 140 135 130 ma precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min) address and control inputs changing once per clock cycle 220 215 200 185 ma active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 175 170 160 145 ma active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) dq,dm,dqs inputs changing twice per clock cycle. address and control inputs changing once per clock cycle 385 380 350 265 ma operating current ( burst mode) i cc4 i ol =0ma , t cc = t cc (min), page burst, all banks activated. dq,dm,dqs inputs changing twice per clock cycle. address and control inputs changing once per clock. 940 935 865 750 ma refresh current i cc5 t rc t rfc 440 435 420 390 ma self refresh current i cc6 -gc cke 0.2v 20 ma -gl 5 ma operating current (4bank interleaving) i cc7 burst length=4 t rc t rc (min). i ol =0ma, t cc = t cc (min). dq,dm,dqs inputs changing twice per clock cycle. address and control inputs changing once per clock cycle 1060 1055 970 950 ma (recommended operating conditions unless otherwise noted, 0 c tc 85 c ) capacitance (v dd =2.0v, t a = 25 c, f=1mhz) parameter symbol min max unit input capacitance ( ck, ck )c in1 2.0 3.0 pf input capacitance (a 0 ~a 11 , ba 0 ~ba 1 )c in2 2.0 3.0 pf input capacitance ( cke, cs , ras ,cas , we ) c in3 2.0 3.0 pf data & dqs input/output capacitance(dq 0 ~dq 31 )c out 3.5 4.5 pf input capacitance(dm0 ~ dm3) c in4 3.5 4.5 pf - 47 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) ac characteristics - i note : 1. the write latency can be set from 1 to 7 clocks. when t he write latency is set to 1 or 2 or 3 clocks(this case can be used regardless of fre quency), the input buffers are turned on dur ing the active commands reducing the latency but added power. when t he write latency is set to 4 ~7 clocks , the input buffers are turned on during the write commands for lower power operation. the write lat ency which is over 4 clocks can be used only in case that write latency*tck is greater than 7ns. 2. a low to high transition on the wdqs line is not allowed in the half clock prior to the write preamble. 3. the last rising edge of wdqs after the write postamble must be riven high by the controller. wdqs can not be pull ed high by the on-die termination alone. 4. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are no t referenced to a specific voltage level, but specify when t he device output is no longer driving (hz) or begins driving (lz). parameter symbol -14 -15 -16 -20 unit note min max min max min max min max dqs out access time from ck t dqsck -0.26 +0.26 -0.26 +0.26 -0.29 +0.29 -0.35 +0.35 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0. 45 0.55 0.45 0.55 tck ck low-level width t cl 0.45 0.55 0.45 0.55 0. 45 0.55 0.45 0.55 tck ck cycle time cl=9 t ck 1.4 3.3 1.4 3.3 - - - - ns cl=8 ----1.63.3--ns cl=7 ------2.03.3ns write latency t wl 5-5-5-4-tck1 dq and dm input hold time relative to dqs t dh 0.18 - 0.18 - 0.20 - 0.25 - ns dq and dm input setup time relative to dqs t ds 0.18 - 0.18 - 0.20 - 0.25 - ns active termination setup time t ats 10-10-10-10-ns active termination hold time t ath 10-10-10-10-ns dqs input high pulse width t dqsh 0.48 0.52 0.48 0.52 0. 48 0.52 0.48 0.52 tck dqs input low pulse widthl t dqsl 0.48 0.52 0.48 0.52 0. 48 0.52 0.48 0.52 tck data strobe edge to dout edge t dqsq - 0.160 - 0.160 - 0.180 - 0.225 ns dqs read preamble t rpre 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck write command to first dqs latching transition t dqss wl-0.2 wl+0.2 wl-0.2 wl+0.2 wl -0.2 wl+0.2 wl-0.2 wl+0.2 tck dqs write preamble t wpre 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 2 dqs write preamble setup time t wpres 0-0-0-0-ns dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 3 half strobe period t hp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin -tck data output hold time from dqs t qh t hp -0.16 - t hp -0.16 - t hp -0.18 - t hp - 0.225 -ns data-out high-impedance window from ck and /ck t hz -0.3 - -0.3 - -0.3 - -0.3 - ns 4 data-out low-impedance window from ck and /ck t lz -0.3 - -0.3 - -0.3 - -0.3 - ns 4 address and control input hold time t ih 0.35 - 0.35 - 0.4 - 0.5 - ns address and control input setup time t is 0.35 - 0.35 - 0.4 - 0.5 - ns address and control input pulse width t ipw 1.0 - 1.0 - 1.1 - 1.3 - ns - 48 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) ac characteristics - ii parameter symbol -14 -15 -16 -20 unit note min max min max min max min max row active time t ras 22 100k 22 100k 19 100k 15 100k tck row cycle time t rc 31-31-27-21-tck refresh row cycle time t rfc 39-39-33-27-tck ras to cas delay for read t rcdr 10-10-9-7-tck ras to cas delay for write t rcdw 6-6-5-4-tck row precharge time t rp 9-9-8-6-tck row active to row active t rrd 8-8-7-5-tck last data in to row precharge @ normal pre- charge t wr 9-9-8-7-tck last data in to row precharge @ auto precharge t wr_a 7777tck last data in to read command t cdlr 5-5-4-3-tck mode register set cycle time t mrd 6-6-5-4-tck auto precharge write recovery time + precharge t dal 18-18-16-13-tck exit self refres h to read command t xsr 20000 - 20000 - 20000 - 20000 - tck power-down exit time t pdex 6tck +tis - 6tck +tis - 6tck +tis - 4tck +tis -tck refresh interval time t ref -7.8-7.8-7.8-7.8us - 49 - 256m gddr3 sdram k4j55323qf-gc rev 1.8 (apr. 2005) package dimensions (fbga) unit : mm 12.0 12.0 0.8 0.8 0.35 0.05 1.40 max |
Price & Availability of K4J55323QF-GC14
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |